Phase locked loops (PLLs) are commonly used in electronic microcontroller systems and other communication systems. Phase locked loops fundamentally function by receiving a predetermined reference frequency and providing a locked output frequency having a frequency which is a predetermined multiple of the reference frequency. A phase detector is typically used to compare the frequency of the reference with the locked output frequency after being divided by the predetermined multiple. The phase detector provides a control signal which is proportional to an error between the two frequencies being compared. The control signal is typically filtered by a filter to derive a control voltage for controlling a voltage controlled oscillator (VCO). The voltage controlled oscillator provides the locked output frequency. A frequency divider circuit is coupled to the VCO and to the phase detector to complete a circuit loop. The frequency divider divides the output signal frequency by the predetermined multiple for use by the phase comparator.
Previously, PLLs have not been very successful in providing both fast startup operation and stable operation because the two characteristics were mutually exclusive. Others have used a filter with a large bandwidth to achieve a locked output frequency quickly. However, the large bandwidth filter may create frequency stability problems. Another PLL technique which has been used is to utilize two filter circuits wherein a first filter has a large bandwidth and is used initially to establish quick circuit operation at a locked frequency and a second filter having a more narrow bandwidth is later substituted for subsequent stable circuit operation. Selection of the filter may be made by either a timed switching arrangement or by software control. A problem with the use of two filters of varying bandwidth is associated with the difficulty of determining when the loop first achieves a lock condition. Software controlled filter systems are typically cumbersome and slow.